Description

Lab 3: Sequential Circuits
Prof. Chun-Yi Lee
Agenda
Lab 3 Outline
Basic questions (1.5%)
Individual assignment
Only demonstration is necessary. Nothing to submit.
Advanced questions (5%)
Group assignment
Demonstration on your FPGA board (In class)
Assignment submission (Submit to eeclass)
Source codes and testbenches
Lab report in PDF
Lab 3 Rules

Lab 3 Submission Requirements
Source codes and testbenches
Please follow the templates EXACTLY
We will test your codes by TAs’ testbenches
Lab 3 report
Please submit your report in a single PDF file
Please draw the block diagrams of your designs using software
Please explain your designs in detail
Please list the contributions of each team member clearly
Please explain how you test your design
What you have learned from Lab 3
Agenda
Basic Questions

Verilog Basic Question 1(Con’t)
Verilog Basic Question 2

11
Verilog Basic Question 2 (Con’t)
Agenda
13
Advanced Questions
14
Verilog Advanced Question 1
15

Verilog Advanced Question 2
First-In First Out (FIFO) Queue
 Write Pointer
ren wen (internal signal)

Read Pointer (internal signal)
Design a circular FIFO that stores eight entries of 8-bit data
The order of the read should follow the FIFO pattern, in which the first data written would be read out first
The behavior of the FIFO
By setting ren=1’b1, the FIFO should output the oldest data to dout . On the other hand, if wen=1’b1, the value of din signal is written into the FIFO. If both ren and wen are set to 1’b1, only the read operation is performed
The FIFO should be able to be written unless it is full, and should be able to be read unless it is empty
Verilog Advanced Question 2 (Con’t)
Error condition
If a read / write is issued to an empty / a full FIFO, the error bit should be set to 1’b1. Otherwise, the read / write is valid and the error bit should be set to 1’b0.
The values of dout
If there’s an error, we do not care about the value of dout
If the FIFO is performing a write operation, we also do not care about the value of dout
If rst_n == 1’b0, empty the FIFO, and set both dout and error to zero
Please note that the values of dout and error should change synchronously, i.e., their values should only change at the positive edges of clk.
Verilog Advanced Question 3

Verilog Advanced Question 3 (Con’t)
Multi-Bank Memory
Bank3
Bank2 Sub- Sub-
Bank1 Sub-Bank Sub-Bank
Bank0 Sub-Bank Sub-Bank Memory Module
Sub-BankSub-Sub-BankSub- In Your Basic
Bank0Sub-BankBank1Sub-Bank Question 2
Sub-Bank Sub-Bank Sub-Bank Sub-Bank
Bank2 Bank3
The most significant four bits of raddr (i.e. raddr[10:7], read address) and waddr (i.e. waddr[10:7], write address) are used to address different sub-banks. For
example, waddr[10:7] == 4’b0110 addresses bank1’s sub-bank2
When wen == 1’b1, write din to Memory[addr]
When ren == 1’b1, output Memory[addr] to dout; otherwise dout = 8’d0
When both wen and ren are 1’b1, they can be serviced simultaneously if they are directed for different sub-banks. Otherwise, only read request is serviced

Verilog Advanced Question 4
Design a Round-Robin FIFO Arbiter based on Advanced Q2
Input: clk, rst_n, wen[3:0], a[7:0], b[7:0], c[7:0], d[7:0] output: valid, dout[7:0]
Four FIFOs in advanced question Q2 are connected to a round robin arbiter, which controls their ren signals to make them output their contents via dout in a round robin fashion.
Verilog Advanced Question 4 (Con’t)
Each FIFO is written independently by setting the corresponding bit in wen to 1’b1, e.g. setting wen to 4’b0001 will write a to FIFO a, 4’b1001 will write d to FIFO d and a to FIFO a
The input data of FIFOs a, b, c and d are supplied via input ports a, b, c, and d, respectively
However, if the FIFO that is being accessed by the arbiter, is also being written or its error signal is 1’b1, the access is considered invalid. In such a situation, the valid and the dout signal should be set to 1’b0 and no data is read out from the FIFO. Otherwise, the read access is valid and valid should be set to 1’b1.
Please note that the values of dout and valid should change synchronously, i.e., their values should only change at the positive edges of clk.
Please refer to the next slide for a sample waveform.

Verilog Advanced Question 5
Verilog Advanced Question 5 (Con’t)
rst_n and enable
When rst_n == 1’b0, resets out to min and direction to 1’b1
When enable == 1’b1, the counter begins its operation. Otherwise, the counter holds its current value
max and min max and min values are the maximum and minimum values for the counter
max > min. Otherwise, the counter holds its current value
When counter > max or counter < min, counter holds its current value
flip
When flip == 1’b1, counter flips its direction
Flip is only one cycle in length
Flip occurs when counter < MAX and counter > MIN

25

Advanced Questions
4-bit Paramterized Ping-Pong Counter on FPGA
Behavior specification
In the beginning, the digits showing on the 7-segment display should be the value of min
Once enable is on, the Ping-Pong Counter starts counting
When enable is off, the Ping-Pong Counter holds its value
The Ping-Pong Counter only counts when max > min
Switches
SW[15] stands for enable
SW[14:11] stand for max
SW[10:7] stand for min

Notes
Be careful that max and min will change during counting
Once the value of the counter is out of range, hold the value and direction
If max == min == output, please hold the output and direction
You MUST add debounce and one-pulse circuits for your buttons
Remember to add debounce and one-pulse circuits to your design
We use the 100MHz clock which is provided by the FPGA board. Please set clk as input and connect it with the W5 port on the FPGA board.
Your counter should count in an observable frequency so that TAs can tell whether your design is correct or not