Description

In this homework, you will learn the following:
⚫ Hspice
⚫ nWave

1. (70%)
(0) EN
(1) NR2
(2) OR2
(3) EO3
(4) AN3
(5) ND2
(6) AN2
(7) EO
(8) DRIVER
(9) IV
(10) FA1

For each cell,
a. Base on the layout view, draw transistor-level and gate-level circuit (NAND2
/ NOR2 / INV) diagrams (using PowerPoint, paint or 手畫)
b. Identify all inputs and outputs
c. List truth table
d. Revise the given netlist file to construct your cells. All PMOS transistors have
width 0.5um and length 0.1um. All NMOS transistors have width 0.25um and length 0.1um. Parameters of the 90nm model file (90nm_bulk.l) must be included during the simulation. The substrate of PMOS is connected to VDD and the substrate of NMOS is connected to VSS.
e. Run Hspice simulation on all possible input combinations. Assume
VDD=1.0V and VSS=0V. Use nWave to verify the truth table. Copy the I/O waveform to your report. State what you have observed.
f. Please discuss the problems you have encountered.

Files that you will need (available on the class website)
HW2_2020.zip includes the following files
⚫ HW2_2020.pdf (this document)
⚫ HW2_tutorial_2020.pdf
⚫ example.sp (CMOS inverter的範例程式)
⚫ 90nm_bulk.l
⚫ Pictures of layouts (in “pic” folder)

Files that you need to submit
⚫ The hard copy of your report (in class)
– List the names of the cells you did in homework in front of the report.
– Attach your HSpice code and waveform results

References
[1] “SPICE,” CIC handout, 2001
[2] ”鳥哥的 Linux 私房菜,” http://linux.vbird.org/

If there’s any workstation account/password problem, please directly contact the workstation administrator，邱茂菱，d01943010@ntu.edu.tw

2. (20%) In Chapter 3, we analyzed the rising and falling delays of a NAND3 gate with fanout h (slide 10 of Chapter 3). Following a similar approach, derive the falling and rising delays of a NOR4 gate.

3. (10%) Determine the activity factors at each node in the following circuit assuming the input probabilities 𝑃𝐴 = 𝑃𝐵 = 𝑃𝐶 = 𝑃𝐷 = 0.5.

11/12 12:00-14:00 @ 博理 215 室