Description

CENG232
Logic Design
Lab 1

1 Introduction
This laboratory aims to get you familiar with basic logic gates and combinational circuit design. You will simplify the circuit that is explained below and draw the circuit using the Logisim tool with the given gates.
2 IC Pool
In this LAB, you will use the following gates to build the circuit:
• 74LS04 (Inverter)
• 74LS08 (AND)
• 74LS32 (OR)
Note that you can use only the given gates. Usage of other gates is NOT allowed.
3 Lab Work
In this assignment, you are expected to perform the operations described in the following section.
3.1 Specifications
Suppose A and B are 2-bit binary input numbers and X, Y and Z are 1-bit binary output numbers. A and B are represented with A1, A0, B1 and B0 bits respectively where A1 and B1 are the most significant bits and A0 and B0 are the least significant bits of the relevant number. Your circuit will take A and B as inputs and generate the outputs X,Y and Z with the following instructions:
(
1
X = A − B < −1
0 otherwise
(
1
Y = A/B is defined and an integer
0 otherwise
(
B) + (B B) + (B
Z =
0 otherwise
You have to use ”input pins” and ”output pins” for your inputs and outputs, respectively, from the Toolbar at the top of Logisim. Set their labels correctly using the following names:
Input pins: A1, A0, B1, B0. Output pins: X, Y, Z.
Please, only set “label” property of the “pin” objects, do not add a “label” object onto the Logisim canvas.
Each pin corresponds to a digit in a 2-bit binary number. If it is set, then the value of the digit is 1 if reset, then the value of the digit is 0. Note that and are logical right and left shift operators respectively. For instance (4=0b100, 2=0b10) 4 1 corresponds to shifting the bits of value 4 one step to right and results in 0b010. Similarly, 22 operation shifts the bits of value 2 two steps to left, which yields 8=0b1000.
We highly recommend you simplify your circuitry as much as possible (via the techniques covered in the lectures) for ease of implementation. If the pandemic measure weren’t in effect, you would be supposed to implement your design on breadboards, and the number of ICs that you’d purchase would be limited, hence it would be inevitable to simplify your circuits.
3.2 Input Output Examples
1. Suppose A1A0 = 00 and B1B0 = 10. In this case, A=0 and B=2 in decimal.
A − B = −2
Since A − B < −1, the output X is 1.
2. Suppose A1A0 = 10 and B1B0 = 01. In this case, A=2 and B=1 in decimal.
A − B = 1
Since A − B < −1 does not hold, the output X is 0.
3. Suppose A1A0 = 01 and B1B0 = 01. In this case, A=1 and B=1 in decimal. A/B = 1
Since A/B is defined and an integer, the output Y is 1.
4. Suppose A1A0 = 01 and B1B0 = 10. In this case, A=1 and B=2 in decimal. A/B = 0.5
Since A/B is not an integer, the output Y is 0.
5. Suppose A1A0 = 01 and B1B0 = 10. In this case, A=1 and B=2 in decimal.
B = 0, B A = 1
B) + (B A)) B) + (B
Since ((A B) + (B A)) B) + (B = 3 does not hold, the output Z is 0.
6. Suppose A1A0 = 01 and B1B0 = 01. In this case, A=1 and B=1 in decimal.
B = 1, B A = 0
B) + (B B) + (B
Since ((A B) + (B B) + (B = 3 holds, the output Z is 1.
4 Deliverables
5 Cheating Policy
All the lab work should be individual and there is a policy of zero tolerance for cheating. See the course website for further information about cheating policy.
6 References
CENG Logism Version.