Description

CENG232
Logic Design
Lab – 4 Part-2

1 Login/Logout System For An Online Game (Teamwork)
This part of the lab will be performed and submitted with your group partner. Only submit a single copy per group.
1.1 Problem Definition
In this part, you are going to implement a login/logout system for a simple online RPG (Role Playing Game) called Heroes of Logic in Verilog. The game consists of different characters with differing attributes. In the game, there are two teams, namely, LogicPower and CengForce. You are expected to implement the login/logout system of this game which is summarized as follows:
1) Players can either login or logout the game in their teams with their user IDs.
2) The capacity of teams is five.
3) Different players can have the same 4-bit code.
4) You should keep count of the current number of players logged in a team. In case a player login/logouts from the game, the number of players for his/her team should be updated.
5) The login of players into the teams are arranged as follows:
a) If the MSB of user ID of a player is 0, the player can login the game only in LogicPower team.
b) If the MSB of user ID of a player is 1, the player can login the game only in CengForce team.
7) In case a player wants to login the game in a team that is allowed, the following should be checked:
8) Initially, number of logged in users in both teams will be 0.
10) If a player is allowed to login the game in a team, his/her user ID will be inserted into the memory of this team.
11) If a player wants to logout the game, his/her user ID will be deleted from the memory of his/her team.
12) There will be four modes in the system:
a) Login Mode:
i) Players can login the game only when the system is in Login Mode.
b) Logout Mode:
i) Only players who are currently logged in a team can logout the game with their user ID. It will not be tested that if a student who is not currently logged in the game can logout or not.
ii) If a player logouts the game, his/her 4-bit user ID recorded will be deleted from the memory of that team.
c) Find Mode: The user ID that is entered will be searched in the memory of the given team.
d) List Mode:
i) It should be indicated if the system is in the list mode.
ii) In this mode, the user IDs that were stored in the given team’s memory will be displayed one by one in every pulse of the CLK. The order of the display is the order of the records in that memory. iii) Empty slots should not be ignored while displaying the user IDs. The empty slots will be shown as “0000”.
13) Initially, each record of the team memories will be ”0000”.
14) ”0000” will not be used as user ID; hence, a player can not have “0000” as his/her user ID.
1.2 Input/Output Specifications
• userID represents 4-bit user ID.
Name Type Size
userID Input 4 bits
Clock (CLK) Input 1 bit
team Input 1 bit
mode Input 2 bits
numPlyLP Output 8 bits
numPlyCF Output 8 bits
teamWng Output 1 bit
capWngLP Output 1 bit
capWngCF Output 1 bit
findRes Output 1 bit
listOut Output 4 bits
listMode Output 1 bit
• CLK is the clock input for the module.
• team is used for the selection of the team. team = 0 ⇒ Team Logic Power team = 1 ⇒ Team Ceng Force
• mode indicates the selected mode among the following 4 modes:
mode = 00 ⇒ Logout mode mode = 01 ⇒ Login mode mode = 10 ⇒ Find mode mode = 11 ⇒ List mode
• numPlyLP, numPlyCF keeps the number of current players already logged in Logic Power and Ceng Force teams, respectively.
• teamWng shows whether the player wants to login to the correct or wrong team.
teamWng = 0 ⇒ Correct team.
teamWng = 1 ⇒ Wrong team.
• capWngLP/capWngCF shows whether Logic Power/Ceng Force team is full/empty or not. capWngLP/capWngCF = 1 ⇒ Logic Power/Ceng Force team is either full or empty. capWngLP/capWngCF = 0 ⇒ otherwise.
• findRes shows whether 4 bit user ID to be searched in the given team memory is found or not.
findRes = 1 ⇒ Found.
findRes = 0 ⇒ Not found.
• listOut shows the user ID in the given team’s memory sequentially each time CLK pulse is given.
• listMode indicates whether the system is in list mode or not.
listMode = 1 ⇒ System is in list mode. listMode = 0 ⇒ Otherwise.
1.3 Sample Input/Output
Between current state and next state, there will be one CLK cycle.
Initial Values:
Team Logic Power Memory Team Ceng Force Memory
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
teamWng capWngLP capWngCF findRes listOut listMode
0 1 1 0 No output 0
a) A player with user ID 1000 wants to login the game in Ceng Force team and the systemallows the login (correct team):
Current State
Team Logic Power Memory Team Ceng Force Memory
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
userID team mode teamWng capWngLP capWngCF findRes listOut listMode
1000 1 01 0 1 1 0 No output 0
Next State
Team Logic Power Memory Team Ceng Force Memory
0000 0000 0000 0000 0000 1000 0000 0000 0000 0000
teamWng capWngLP capWngCF findRes listOut listMode
0 1 0 0 No output 0
Current State
Team Logic Power Memory Team Ceng Force Memory
0001 0010 0100 0101 0110 1000 1010 1011 1100 1111
userID team mode teamWng capWngLP capWngCF findRes listOut listMode
1001 0 01 0 1 1 0 No output 0
Next State
Team Logic Power Memory Team Ceng Force Memory
0001 0010 0100 0101 0110 1000 1010 1011 1100 1111
teamWng capWngLP capWngCF findRes listOut listMode
1 1 1 0 No output 0
c) A player with user ID 0010 wants to login the game in Logic Power team and the systemdoes not allow login since a player with same user ID is already logged in:
Current State
Team Logic Power Memory Team Ceng Force Memory
0001 0010 0100 0101 0110 1000 1010 1011 1100 0000
userID team mode teamWng capWngLP capWngCF findRes listOut listMode
0010 0 01 0 1 0 0 No output 0
Next State
Team Logic Power Memory Team Ceng Force Memory
0001 0010 0100 0101 0110 1000 1010 1011 1100 0000
teamWng capWngLP capWngCF findRes listOut listMode
0 1 0 0 No output 0
Current State
Team Logic Power Memory Team Ceng Force Memory
0001 0010 0100 0101 0110 1000 1010 0000 1100 1011
userID team mode teamWng capWngLP capWngCF findRes listOut listMode
1001 1 01 0 1 0 0 No output 0
Next State
Team Logic Power Memory Team Ceng Force Memory
0001 0010 0100 0101 0110 1000 1010 1001 1100 1011
teamWng capWngLP capWngCF findRes listOut listMode
0 1 1 0 No output 0
e) A player with user ID 0100 logouts the game and the record is deleted from LogicPower Memory:
Current State
Team Logic Power Memory Team Ceng Force Memory
0001 0010 0100 0101 0110 1000 1010 0000 1100 1011
userID team mode teamWng capWngLP capWngCF findRes listOut listMode
0100 0 00 0 1 0 0 No output 0
Next State
Team Logic Power Memory Team Ceng Force Memory
0001 0010 0000 0101 0110 1000 1010 0000 1100 1011
teamWng capWngLP capWngCF findRes listOut listMode
0 0 0 0 No output 0
f) Listing the user IDs in Ceng Force memory in list mode:
Current State
Team Logic Power Memory Team Ceng Force Memory
0001 0010 0100 0101 0110 1000 1010 0000 1100 1011
team mode teamWng capWngLP capWngCF findRes listOut listMode
1 11 0 1 0 0 No output 0
Next State
Team Logic Power Memory Team Ceng Force Memory
0001 0010 0100 0101 0110 1000 1010 0000 1100 1011
teamWng capWngLP capWngCF findRes listOut listMode
0 1 0 0 1000 1
In every CLK pulse, the listOut will display the next record. (1010, 0000, 1100, 1011). After all the records are displayed, it will start displaying from the beginning.
g) Searching the user ID 0100 in Logic Power memory:
Current State
Team Logic Power Memory Team Ceng Force Memory
0001 0010 0100 0101 0110 1000 1010 0000 1100 1011
team mode teamWng capWngLP capWngCF findRes listOut listMode
0 10 0 1 0 0 No output 0
Next State
Team Logic Power Memory Team Ceng Force Memory
0001 0010 0100 0101 0110 1000 1010 0000 1100 1011
teamWng capWngLP capWngCF findRes listOut listMode
0 1 0 1 No output 0
1.4 FPGA Implementation
You will be provided with a Board232.v file (and a ready-to-use Xilinx project), which will bind inputs and outputs of the FPGA board with your Verilog module. You are required to test your Verilog module on the FPGA boards.
Name FPGA Board Description
userID SW7,SW6,SW5,SW4 Left-most 4 switches (A)
Clock (CLK) BTN0 Right-most button (C)
team SW0 Right-most switch (B)
mode SW2,SW1 The next 2 switches next to SW0 (B)
teamWng LD7 Left-most led (F)
capWngLP LD0 Right-most led (G)
capWngCF LD1 The led next to LD0 (G)
findRes LD2 The led next to LD1 (G)
listOut 7-segment display (D) **
listMode LD4 The led next to LD3 (E)
**:Each individual bit will be displayed in each component of the 7-segment display (D)

1.5 Deliverables
• This part is supposed to be done with your group partner. Make sure both of you take roles in implementation of the project. Any kind of inter-group cheating is not allowed.
• Use the newsgroup metu.ceng.course.232 for any questions regarding the homework.