Description

Introduction: For this project you are to design a 64-bit ARM CPU with Pipelining. The CPU instructions to be implemented are the same as project 3. Your pipelined CPU will have 1 delay slot after each load and branch instruction, as discussed in class. It is also responsible for covering data forwarding. Note that you should carefully consider how data forwarding and branches will interact. You will use your three previous projects (the file register, the ALU, and the single cycle CPU) so you will need to have these fully functional. As with project 3, we will provide you with sample instruction sequences with which to test your CPU, and you will have to display the modified registers at the end of the execution. Please remember the rules from previous labs as well.

1.) What happens if an instruction writes back to register 31, which is required to always be 0 regardless of what is written to that register?
4.) Not all instructions write registers, and different instructions have register IDs at different places in the instruction word. These should be carefully considered.

TURN-IN

For this lab you will turn in the code electronically and demo the functionality of your
CPU to the TAs. Note that all of the memories and programs from lab #3 work for this CPU as well (the programs were written to be mostly insensitive to pipelining, though some changes in output will occur).
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